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Full discrete 74LS138

2026-09-26 07:00:00 | pcba-mkr

① When one selection terminal (E1) is at a high level, and the other two selection terminals ( ) and ( ) are at low levels, the binary encoding of the address terminals (A0, A1, A2) can be translated into low-level signals at the corresponding output terminals Y0 to Y7. (That is, the output is the inverse of Y0 to Y7.) For example: When A2A1A0 = 110, then the output terminal Y6 will output a low-level signal.

② Using E1, E2, and E3, it can be cascaded to expand into a 24-line decoder; if an inverter is externally connected, it can also be cascaded to expand into a 32-line decoder.

③ If one of the selection terminals is used as a data input terminal, the 74LS138 can also be used as a data distributor.

④ It can be used in the decoding circuit of 8086 to expand the memory.